| commit | 66dbb0c5d67279722fcbcb547d9c6b61e606d50e | |
| author | Vaibhav Shankar <vaibhav.shankar@intel.com> | |
| Thu, 11 Jan 2018 18:27:50 +0000 (11 10:27 -0800) | ||
| committer | Martin Roth <martinroth@google.com> | |
| Tue, 23 Jan 2018 05:43:10 +0000 (23 05:43 +0000) | ||
| tree | df3a9d8318ff4e170fa2192678d6ff8682975b3b | treesnapshot (tar.gz zip) |
| parent | 73f19dca386d775a880bdc945efaa6b9c77d9e94 | commitdiff |
src/soc/intel/cannonlake: Update C-state latency control limits
PC10 is a necessary condition for S0ix entry. With the current C-state limits,
CPU fails to enter PC10 during S0ix. C-state Latency control limits
have to be tuned to new values for PC10 entry.
Change-Id: I0f5227f9c3c10c5a9e335ab118eb0ec185445374
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/23220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
PC10 is a necessary condition for S0ix entry. With the current C-state limits,
CPU fails to enter PC10 during S0ix. C-state Latency control limits
have to be tuned to new values for PC10 entry.
Change-Id: I0f5227f9c3c10c5a9e335ab118eb0ec185445374
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/23220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| src/soc/intel/cannonlake/cpu.c | diffblobblamehistory | |
| src/soc/intel/cannonlake/include/soc/cpu.h | diffblobblamehistory |