ACPI: Refactor ChromeOS specific ACPI GNVS
commit66c6413c69abb7335efc4ea07f4c811c042704b6
authorKyösti Mälkki <kyosti.malkki@gmail.com>
Sat, 19 Dec 2020 14:19:44 +0000 (19 16:19 +0200)
committerKyösti Mälkki <kyosti.malkki@gmail.com>
Mon, 18 Jan 2021 18:02:27 +0000 (18 18:02 +0000)
tree06d58b85da4c779cca7b78e33a069ea03a4e69e4
parentc4a6628a6fe4f5400b7abe1478d0b0b21cb8200f
ACPI: Refactor ChromeOS specific ACPI GNVS

The layout of GNVS has expectation for a fixed size
array for chromeos_acpi_t. This allows us to reduce
the exposure of <chromeos/gnvs.h>.

If chromeos_acpi_t was the last entry in struct global_nvs
padding at the end is also removed.

If device_nvs_t exists, place a properly sized reserve for
chromeos_acpi_t in the middle.

Allocation from cbmem is adjusted such that it matches exactly
the OperationRegion size defined inside the ASL.

Change-Id: If234075e11335ce958ce136dd3fe162f7e5afdf7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
19 files changed:
src/acpi/chromeos-gnvs.c
src/acpi/gnvs.c
src/acpi/nvs.c
src/include/acpi/acpi_gnvs.h
src/soc/amd/picasso/include/soc/nvs.h
src/soc/amd/stoneyridge/include/soc/nvs.h
src/soc/intel/apollolake/include/soc/nvs.h
src/soc/intel/baytrail/include/soc/nvs.h
src/soc/intel/braswell/include/soc/nvs.h
src/soc/intel/broadwell/include/soc/nvs.h
src/soc/intel/common/block/include/intelblocks/nvs.h
src/soc/intel/skylake/include/soc/nvs.h
src/southbridge/intel/bd82x6x/include/soc/nvs.h
src/southbridge/intel/i82801gx/include/soc/nvs.h
src/southbridge/intel/i82801ix/include/soc/nvs.h
src/southbridge/intel/i82801jx/include/soc/nvs.h
src/southbridge/intel/ibexpeak/include/soc/nvs.h
src/southbridge/intel/lynxpoint/include/soc/nvs.h
src/vendorcode/google/chromeos/gnvs.h