| commit | 66579d4e362bb640a9c9e2d960d72c6c37ff67cc | |
| author | Felix Singer <felix.singer@secunet.com> | |
| Mon, 6 Apr 2020 08:45:25 +0000 (6 10:45 +0200) | ||
| committer | Nico Huber <nico.h@gmx.de> | |
| Tue, 7 Apr 2020 11:15:13 +0000 (7 11:15 +0000) | ||
| tree | 196b212d8b461b6cd0dbeadcd25fb272ab5079a3 | treesnapshot (tar.gz zip) |
| parent | ecaa2d4741696ab0228500fd170e58ee4d268353 | commitdiff |
sb/intel/bd82x6x/sata: Don't hard-code values
The interrupt line registers are configured in a central place,
pch_pirq_init() in `lpc.c`, according to the PIRQ configuration.
Hardcoding values here makes no sense.
Change-Id: Ide5f101b2e5bda84f3c2ff8c8ca636b8233bb948
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The interrupt line registers are configured in a central place,
pch_pirq_init() in `lpc.c`, according to the PIRQ configuration.
Hardcoding values here makes no sense.
Change-Id: Ide5f101b2e5bda84f3c2ff8c8ca636b8233bb948
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
| src/southbridge/intel/bd82x6x/pch.h | diffblobblamehistory | |
| src/southbridge/intel/bd82x6x/sata.c | diffblobblamehistory |