| commit | 65adc701652e4ad9e9cf26d82dcc7eaeae52d898 | |
| author | Angel Pons <th3fanbus@gmail.com> | |
| Sun, 14 Nov 2021 14:34:02 +0000 (14 15:34 +0100) | ||
| committer | Felix Singer <felixsinger@posteo.net> | |
| Fri, 19 Nov 2021 13:54:48 +0000 (19 13:54 +0000) | ||
| tree | 50edcdee93b023832a0abc1f4ad7c949a8707e1c | treesnapshot (tar.gz zip) |
| parent | c9bc7a7591d9b667e4249b98e4037d6e7239f2e8 | commitdiff |
util/inteltool: Add ICH10D PCI ID
Add the PCI device ID for the ICH10D southbridge. While we're at it,
also fix up whitespace in inteltool.h of an adjacent definition.
Change-Id: I98d88a9ce27d3ddaafd7123ee51b2111a8bef019
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Add the PCI device ID for the ICH10D southbridge. While we're at it,
also fix up whitespace in inteltool.h of an adjacent definition.
Change-Id: I98d88a9ce27d3ddaafd7123ee51b2111a8bef019
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>