{cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriate
commit654cc2fe109ea1be4d22447b3d0e6eb22a75b550
authorNico Huber <nico.h@gmx.de>
Sun, 27 May 2018 11:52:28 +0000 (27 13:52 +0200)
committerNico Huber <nico.h@gmx.de>
Thu, 31 May 2018 15:10:21 +0000 (31 15:10 +0000)
treedf38c7f7fae159a0549c31acd39b4dd8648fc538
parent6197b7698875271a2b72e730040ec7e9260a454c
{cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriate

Change-Id: Ibc2392cd2a00fde3e15dda4d44c8b6874d7ac8a3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
src/cpu/intel/car/romstage.c
src/cpu/intel/fsp_model_406dx/bootblock.c
src/drivers/intel/fsp1_0/cache_as_ram.inc
src/northbridge/intel/gm45/ram_calc.c
src/northbridge/intel/i945/ram_calc.c
src/northbridge/intel/nehalem/ram_calc.c
src/northbridge/intel/pineview/ram_calc.c
src/northbridge/intel/sandybridge/ram_calc.c
src/northbridge/intel/x4x/ram_calc.c
src/soc/intel/fsp_baytrail/bootblock/bootblock.c