| commit | 6362de3829c1762632e3aa16b1af0fd0a9a1e625 | |
| author | Subrata Banik <subrata.banik@intel.com> | |
| Thu, 30 Jul 2020 06:01:55 +0000 (30 11:31 +0530) | ||
| committer | Subrata Banik <subrata.banik@intel.com> | |
| Sat, 1 Aug 2020 06:55:36 +0000 (1 06:55 +0000) | ||
| tree | 02298fb9fa0c11fc74dc67743a2cdbeaf38d07c5 | treesnapshot (tar.gz zip) |
| parent | 46f807324916f223282e5c8fee1bfe4595eeb1f2 | commitdiff |
soc/intel/{icl,jsl,tgl}: Remove SkipMpInit UPD as deprecated
FSP default UPD for SkipMpInit is set to 0 which refers to run CPU
feature programming on all cores (BSP + APs).
Setting SkipMpInit=1 is not recommended as it will only limit CPU
feature programming on BSP.
TEST=Able to perform CPU feature programming by FSP on all cores
using external MP PPI services.
Change-Id: I22e70f5f15e53c5fabd78cc3698c4d718b607af6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
FSP default UPD for SkipMpInit is set to 0 which refers to run CPU
feature programming on all cores (BSP + APs).
Setting SkipMpInit=1 is not recommended as it will only limit CPU
feature programming on BSP.
TEST=Able to perform CPU feature programming by FSP on all cores
using external MP PPI services.
Change-Id: I22e70f5f15e53c5fabd78cc3698c4d718b607af6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
| src/soc/intel/icelake/fsp_params.c | diffblobblamehistory | |
| src/soc/intel/jasperlake/fsp_params.c | diffblobblamehistory | |
| src/soc/intel/tigerlake/fsp_params.c | diffblobblamehistory |