| commit | 624bf72709423d72acda107ed6d00b945068268d | |
| author | Angel Pons <th3fanbus@gmail.com> | |
| Sat, 5 Nov 2022 08:08:49 +0000 (5 09:08 +0100) | ||
| committer | Eric Lai <eric_lai@quanta.corp-partner.google.com> | |
| Mon, 7 Nov 2022 02:29:09 +0000 (7 02:29 +0000) | ||
| tree | db3ab9177880545ee0b20fd56b7506b4789b3b6a | treesnapshot (tar.gz zip) |
| parent | 6ec48057d0f64c4595758df166dc80fb4ae84ba2 | commitdiff |
soc/intel/cannonlake: Fix GPIO reset mapping
According to document 337348-001 (Intel® 300 Series and Intel® C240
Series Chipset Family Platform Controller Hub Datasheet - Volume 2
of 2), the only GPIOs that support PWROK reset are those in the GPD
group. The mappings themselves are correct, but they're assigned to
the wrong communities.
Change-Id: Ib586c987f768ddff31b053f4c108a8526326a7dc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69214
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
According to document 337348-001 (Intel® 300 Series and Intel® C240
Series Chipset Family Platform Controller Hub Datasheet - Volume 2
of 2), the only GPIOs that support PWROK reset are those in the GPD
group. The mappings themselves are correct, but they're assigned to
the wrong communities.
Change-Id: Ib586c987f768ddff31b053f4c108a8526326a7dc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69214
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
| src/soc/intel/cannonlake/gpio_cnp_h.c | diffblobblamehistory |