| commit | 601a971545e30057dda17e77de854a0bd1f5f226 | |
| author | Felix Held <felix-coreboot@felixheld.de> | |
| Wed, 8 Dec 2021 15:13:01 +0000 (8 16:13 +0100) | ||
| committer | Felix Held <felix-coreboot@felixheld.de> | |
| Wed, 15 Dec 2021 22:37:42 +0000 (15 22:37 +0000) | ||
| tree | 8b8fbff2b80694b40eeded8ba1fc5dc0e0126b10 | treesnapshot (tar.gz zip) |
| parent | 19ad39b7f260c4c27b4cb74ae12215f57a750fda | commitdiff |
soc/amd/common/include/spi: fix SPI_FIFO_LAST_BYTE define
The last byte of the SPI FIFO SPI_FIFO_LAST_BYTE is at offset 0xc6 of
the SPI controller's MMIO region for Stoneyridge and Picasso. Both
SPI_FIFO_LAST_BYTE and SPI_FIFO_DEPTH had an off-by-one error that ended
up cancelling out each other, so the resulting value for SPI_FIFO_DEPTH
isn't changed.
TEST=Timeless build results in identical image for Mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1676be902ccf57e2e9f69d81251b4315866a0628
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The last byte of the SPI FIFO SPI_FIFO_LAST_BYTE is at offset 0xc6 of
the SPI controller's MMIO region for Stoneyridge and Picasso. Both
SPI_FIFO_LAST_BYTE and SPI_FIFO_DEPTH had an off-by-one error that ended
up cancelling out each other, so the resulting value for SPI_FIFO_DEPTH
isn't changed.
TEST=Timeless build results in identical image for Mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1676be902ccf57e2e9f69d81251b4315866a0628
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
| src/soc/amd/common/block/include/amdblocks/spi.h | diffblobblamehistory |