| commit | 5fdf2760a5952df22e5b331bc4f62082d8cec1bc | |
| author | John Zhao <john.zhao@intel.com> | |
| Tue, 28 Jul 2020 19:51:53 +0000 (28 12:51 -0700) | ||
| committer | Nick Vaccaro <nvaccaro@google.com> | |
| Wed, 29 Jul 2020 22:46:45 +0000 (29 22:46 +0000) | ||
| tree | c62a5da01564666de47a4b0f2f4246a4e76b21f0 | treesnapshot (tar.gz zip) |
| parent | bd615d6f9379cc454c728c8f79f13612f3fb7a19 | commitdiff |
mb/google/volteer: Update TCSS D3Hot and D3Cold configuration
It is expected TCSS D3Hot is enabled. D3Cold configuration is
through SoC stepping determination. D3Cold is disabled on pre-QS
platform and enabled on QS platform.
BUG=None
TEST=Verified both of TCSS D3Hot and D3Cold configuration on Volteer.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I9a8b838dcb449ca78d15b18543d97d84b59417ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44004
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It is expected TCSS D3Hot is enabled. D3Cold configuration is
through SoC stepping determination. D3Cold is disabled on pre-QS
platform and enabled on QS platform.
BUG=None
TEST=Verified both of TCSS D3Hot and D3Cold configuration on Volteer.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I9a8b838dcb449ca78d15b18543d97d84b59417ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44004
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| src/mainboard/google/volteer/variants/baseboard/devicetree.cb | diffblobblamehistory |