| commit | 5bb9fd6e4dae32f86a07676228034d3828820037 | |
| author | Kevin O'Connor <kevin@koconnor.net> | |
| Wed, 19 Jan 2011 06:32:35 +0000 (19 06:32 +0000) | ||
| committer | Stefan Reinauer <stepan@openbios.org> | |
| Wed, 19 Jan 2011 06:32:35 +0000 (19 06:32 +0000) | ||
| tree | 9933b8327f3af0ce6814d5402ce798a3720d273e | treesnapshot (tar.gz zip) |
| parent | 4adc9eb60047e7dc3a7921793c489fff4fe3fc57 | commitdiff |
Now that the VIA code is run above 1Meg (like other boards), it should
cache that range instead of the first 1Meg. This reduces boot time by
about 1 second on epia-cn.
This patch also adds a MTRRphysMaskValid bit definition.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6272 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
cache that range instead of the first 1Meg. This reduces boot time by
about 1 second on epia-cn.
This patch also adds a MTRRphysMaskValid bit definition.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6272 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
| src/cpu/via/car/cache_as_ram.inc | diffblobblamehistory | |
| src/cpu/x86/mtrr/mtrr.c | diffblobblamehistory | |
| src/include/cpu/x86/mtrr.h | diffblobblamehistory |