baytrail: add support for routing gpio pins to smi/sci
commit59a4cd55782f1148d37f0c2408657ba93deefc86
authorAaron Durbin <adurbin@chromium.org>
Mon, 11 Nov 2013 18:09:28 +0000 (11 12:09 -0600)
committerAaron Durbin <adurbin@google.com>
Tue, 6 May 2014 16:39:22 +0000 (6 18:39 +0200)
treeec8afec917b945d042b753a4043219a49798bb0c
parent997d25219b67704ba497a3d67f392a8a743a1782
baytrail: add support for routing gpio pins to smi/sci

In order for gpio pins to trigger an smi/sci the GPIO_ROUT
register needs to be set accordingly. For SMI, the ALT_GPIO_SMI
register needs to be enabled for each gpio as well.

The first 8 gpios from the suspend and core well are the only gpios
that can trigger an SMI or SCI. The settings for the GPIO_ROUT
and ALT_GPIO_SMI register are not commited until the SMM settings
are enabled in the southcluster.

BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted. Manually triggered SCI by changing GPE0a_EN
     and toggling PCH_WAKE_L on the EC console.

Change-Id: Id79b70084edc39fc047475e984494c224bd75d6d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176390
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4957
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
src/soc/intel/baytrail/baytrail/gpio.h
src/soc/intel/baytrail/baytrail/pmc.h
src/soc/intel/baytrail/baytrail/smm.h
src/soc/intel/baytrail/gpio.c
src/soc/intel/baytrail/smm.c