| commit | 580bc412c7449a3592e80ac737c3492af6594dfa | |
| author | Lijian Zhao <lijian.zhao@intel.com> | |
| Wed, 4 Oct 2017 20:43:47 +0000 (4 13:43 -0700) | ||
| committer | Aaron Durbin <adurbin@chromium.org> | |
| Wed, 18 Oct 2017 19:46:10 +0000 (18 19:46 +0000) | ||
| tree | 99907980f2b3c3ccd064a1894da90b81857ff97b | treesnapshot (tar.gz zip) |
| parent | 6cf501c3ae0278092cb76ccab015ad891af1fd48 | commitdiff |
soc/intel/cannonlake: Update PCIE CLKREQ programing
UPD of PCI express clock request was updated in FSP 7.0.14.11,
change that in coreboot accordingly.
TEST=NONE
Change-Id: I2261deccfb489c0de577d580997744a484f07a04
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21878
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
UPD of PCI express clock request was updated in FSP 7.0.14.11,
change that in coreboot accordingly.
TEST=NONE
Change-Id: I2261deccfb489c0de577d580997744a484f07a04
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21878
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>