| commit | 50198c117839ee01c331a827dc57b6293c989f34 | |
| author | Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> | |
| Mon, 31 Oct 2016 17:48:43 +0000 (31 10:48 -0700) | ||
| committer | Martin Roth <martinroth@google.com> | |
| Mon, 7 Nov 2016 19:15:13 +0000 (7 20:15 +0100) | ||
| tree | da689ef8b42bc4e4449ac980d9c4e2fbb4e5d7e7 | treesnapshot (tar.gz zip) |
| parent | 37742f6870ec1d4b860769db25ef665cdb7c1615 | commitdiff |
mainboard/google/reef: update DMIC related pins configuration
CLK_B1(GPIO_80) and DATA_2(GPIO_83) pins needs to be
configured as native mode to use them for DMIC record
on other potential DMIC's.
DMIC blobs configure the clocks. For stereo & quad channel
record, both CLK_A1 and CLK_B1 are enabled.
For mono channel record, only CLK_A1 is enabled.
BUG=chrome-os-partner:56918
BRANCH=None
TEST=During DMIC record, check CLK_B1 and DATA_2 lines
Change-Id: I838009b85190de5360d593238e48c9593c1dc43a
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/17199
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
CLK_B1(GPIO_80) and DATA_2(GPIO_83) pins needs to be
configured as native mode to use them for DMIC record
on other potential DMIC's.
DMIC blobs configure the clocks. For stereo & quad channel
record, both CLK_A1 and CLK_B1 are enabled.
For mono channel record, only CLK_A1 is enabled.
BUG=chrome-os-partner:56918
BRANCH=None
TEST=During DMIC record, check CLK_B1 and DATA_2 lines
Change-Id: I838009b85190de5360d593238e48c9593c1dc43a
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/17199
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| src/mainboard/google/reef/variants/baseboard/gpio.c | diffblobblamehistory |