| commit | 4f61f56be101d472990d631ab592f328117d5dbc | |
| author | Subrata Banik <subrata.banik@intel.com> | |
| Thu, 4 Jul 2019 10:56:58 +0000 (4 16:26 +0530) | ||
| committer | Subrata Banik <subrata.banik@intel.com> | |
| Sat, 6 Jul 2019 03:22:31 +0000 (6 03:22 +0000) | ||
| tree | faa9a7cea94214b1e84617193c5cc661d00f1bd0 | treesnapshot (tar.gz zip) |
| parent | 65f03b7c42152188fbd5ac13cea05aaeb953df31 | commitdiff |
soc/intel/common/block/sata: Convert DWORD width Read/Write to BYTE width
As per EDS Sata port implemented register is byte width (bits[3:0]) hence
converting required DWORD based read/write to BYTE width read/write.
TEST=Able to boot from SATA device on CML hatch.
Change-Id: I545b823318bae461137d41a4490117eba7c87330
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34070
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As per EDS Sata port implemented register is byte width (bits[3:0]) hence
converting required DWORD based read/write to BYTE width read/write.
TEST=Able to boot from SATA device on CML hatch.
Change-Id: I545b823318bae461137d41a4490117eba7c87330
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34070
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| src/soc/intel/common/block/sata/sata.c | diffblobblamehistory |