| commit | 4f14cd8a39e65811af08296633842289efa42927 | |
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | |
| Wed, 18 Dec 2019 17:40:48 +0000 (18 19:40 +0200) | ||
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | |
| Thu, 19 Dec 2019 19:31:08 +0000 (19 19:31 +0000) | ||
| tree | 1cece9915f897af008d2d83701088b3054c4ab93 | treesnapshot (tar.gz zip) |
| parent | 6766f4fd046604e6376c9769cd5f8357dec6a80a | commitdiff |
arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE
If stage cache is enabled, we should not allow S3 resume
to load firmware from non-volatile memory.
This also adds board reset for failing to load postcar
from stage cache.
Change-Id: Ib6cc7ad0fe9dcdf05b814d324b680968a2870f23
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If stage cache is enabled, we should not allow S3 resume
to load firmware from non-volatile memory.
This also adds board reset for failing to load postcar
from stage cache.
Change-Id: Ib6cc7ad0fe9dcdf05b814d324b680968a2870f23
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>