| commit | 4cde9784e01b6024e90c4fe5f1966d91e153707c | |
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | |
| Sat, 13 Jun 2015 00:43:38 +0000 (12 19:43 -0500) | ||
| committer | Patrick Georgi <pgeorgi@google.com> | |
| Fri, 23 Oct 2015 18:02:52 +0000 (23 20:02 +0200) | ||
| tree | 93f56cca8ddbfda181a431fcbc75cfdb889c0ad6 | treesnapshot (tar.gz zip) |
| parent | a690a78cdacf83badeac6fd62c0ea7033b7c789c | commitdiff |
southbridge/amd/sr5650: Fix GPP3a link training in higher width modes
Change-Id: I7503ae42eb8bc91411413ef2cc7e7a723df7091a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11990
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Tested-by: build bot (Jenkins)
Change-Id: I7503ae42eb8bc91411413ef2cc7e7a723df7091a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11990
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Tested-by: build bot (Jenkins)
| src/southbridge/amd/sr5650/pcie.c | diffblobblamehistory |