| commit | 4b10dec1a66122b515b2191f823d7fd379ec655f | |
| author | Alexandru Gagniuc <mr.nuke.me@gmail.com> | |
| Sat, 14 Feb 2015 08:00:32 +0000 (14 02:00 -0600) | ||
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | |
| Sat, 14 Feb 2015 21:54:01 +0000 (14 22:54 +0100) | ||
| tree | e80d293bd0d0d346f920d9735278b16fee55b7b3 | treesnapshot (tar.gz zip) |
| parent | 24501cae529a51ab9304721be0ec60384ab81ee0 | commitdiff |
cpu/allwinner/a10/Kconfig: Link ramstage at base of SDRAM
The default linking behavior of ramstage was changed in commit
* 8f99378 ARMv7/Exynos: Fix memory location assumptions
However, that commit failed to address the issue of maintaining
linking behavior on non-Exynos chips. As a result we ended up
linking ramstage at address 0, which is outside of SDRAM.
Explicitly link ramstage at SDRAM base for A10. This patch does not
address the issue on other chips that were broken by commit 8f99378.
Change-Id: I90fa41d3eabf110b5ab24c31b78ac6d0474e4083
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8443
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The default linking behavior of ramstage was changed in commit
* 8f99378 ARMv7/Exynos: Fix memory location assumptions
However, that commit failed to address the issue of maintaining
linking behavior on non-Exynos chips. As a result we ended up
linking ramstage at address 0, which is outside of SDRAM.
Explicitly link ramstage at SDRAM base for A10. This patch does not
address the issue on other chips that were broken by commit 8f99378.
Change-Id: I90fa41d3eabf110b5ab24c31b78ac6d0474e4083
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8443
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
| src/cpu/allwinner/a10/Kconfig | diffblobblamehistory |