| commit | 4af0adb443afaed32369fe7a9eb91ff93549ea26 | |
| author | Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> | |
| Sat, 29 Feb 2020 08:32:23 +0000 (29 00:32 -0800) | ||
| committer | Patrick Georgi <pgeorgi@google.com> | |
| Wed, 4 Mar 2020 10:38:05 +0000 (4 10:38 +0000) | ||
| tree | b9209c9ff8309288b0f44f510656076b804684ff | treesnapshot (tar.gz zip) |
| parent | fdccfc62676719ff4fa09c9aa485a96fa7e818f7 | commitdiff |
soc/intel/tigerlake: Update SerialIoUart settings for Tiger Lake
update SerialIoUartAutoFlow settings for Tiger Lake platform.
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I5ff2c63857a868ca4ed72c6d93bf518e085b8879
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39169
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
update SerialIoUartAutoFlow settings for Tiger Lake platform.
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I5ff2c63857a868ca4ed72c6d93bf518e085b8879
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39169
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| src/soc/intel/tigerlake/fsp_params_tgl.c | diffblobblamehistory |