| commit | 4adc8cdd185f46cd62f3bd17188761d3b0b1d87d | |
| author | Marc Jones <marc.jones@se-eng.com> | |
| Wed, 31 Oct 2012 22:24:37 +0000 (31 16:24 -0600) | ||
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | |
| Mon, 12 Nov 2012 03:23:56 +0000 (12 04:23 +0100) | ||
| tree | 6bef9a659fea70f23a42d0c18d81ec3eef685150 | treesnapshot (tar.gz zip) |
| parent | 2a700ec16322561ad487e6ef1ae8878f9a7e4357 | commitdiff |
Add bd82x6x mainboards ASPM overrides.
The Intel PCH can override the ASPM settings via the MPC2 register.
Add a chip override for F0-F7. Mainboards may implement this as
needed.
This also fixes the final PM setup being done too early. It was
being done prior to the PCIe ASPM setup, which happens in the
bridge scan.
Change-Id: Idf2d2374899873fc6b1a2b00abdb683ea9f5bd6b
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1796
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The Intel PCH can override the ASPM settings via the MPC2 register.
Add a chip override for F0-F7. Mainboards may implement this as
needed.
This also fixes the final PM setup being done too early. It was
being done prior to the PCIe ASPM setup, which happens in the
bridge scan.
Change-Id: Idf2d2374899873fc6b1a2b00abdb683ea9f5bd6b
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1796
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
| src/southbridge/intel/bd82x6x/chip.h | diffblobblamehistory | |
| src/southbridge/intel/bd82x6x/pcie.c | diffblobblamehistory |