| commit | 49e0510d57e47e8b6013afd6699d87bd4da9a693 | |
| author | Aamir Bohra <aamir.bohra@intel.com> | |
| Mon, 29 Oct 2018 06:24:19 +0000 (29 11:54 +0530) | ||
| committer | Subrata Banik <subrata.banik@intel.com> | |
| Fri, 2 Nov 2018 03:20:39 +0000 (2 03:20 +0000) | ||
| tree | 73ef3aa51bb8edad52231bee64932d2b2fa39277 | treesnapshot (tar.gz zip) |
| parent | 167a512d84c587c702cc0ed8918c00a2e225bac0 | commitdiff |
mainboard/intel/icelake_rvp: Add ICL flash layout to support IFWI 1.6
Modify flash layout to match ICL-IFWI layout for early SoC PO support
Flash Reg 0: Descriptor [0x0 - 0xFFF]
Flash Reg 1: BIOS [0x400000 - 0xFFFFFF]
Flash Reg 2: IFWI (consist of ME primary & secondary partition and PMC FW)
[0x81000 - 0x3FFFFF]
Flash Reg 8: EC (applicable for Intel RVP with internal EC support)
[0x1000 - 0x80FFF]
Change-Id: I462a384739b5972d9a59569ffdcadba7cdef6a81
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/29316
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Modify flash layout to match ICL-IFWI layout for early SoC PO support
Flash Reg 0: Descriptor [0x0 - 0xFFF]
Flash Reg 1: BIOS [0x400000 - 0xFFFFFF]
Flash Reg 2: IFWI (consist of ME primary & secondary partition and PMC FW)
[0x81000 - 0x3FFFFF]
Flash Reg 8: EC (applicable for Intel RVP with internal EC support)
[0x1000 - 0x80FFF]
Change-Id: I462a384739b5972d9a59569ffdcadba7cdef6a81
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/29316
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| src/mainboard/intel/icelake_rvp/chromeos.fmd | diffblobblamehistory |