| commit | 46bfce335337a11a9b48c496672bd6020e8dbaeb | |
| author | Elyes HAOUAS <ehaouas@noos.fr> | |
| Wed, 15 Jun 2016 17:05:11 +0000 (15 19:05 +0200) | ||
| committer | Martin Roth <martinroth@google.com> | |
| Fri, 24 Jun 2016 16:08:04 +0000 (24 18:08 +0200) | ||
| tree | a759a164557a157d100c8059668626209d9344b4 | treesnapshot (tar.gz zip) |
| parent | a1850bafbffd147bd5aad8b2a6463f40cc28ddec | commitdiff |
spd: Add module voltage for 1.8V
Add SSTL 1.8 V Interface Level as specified in
JEDEC_DDR2_SPD_Specification_ Rev1.3, page 10.
Change-Id: I0112a85f557826b629109e212dbbc752aeda305d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15202
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Add SSTL 1.8 V Interface Level as specified in
JEDEC_DDR2_SPD_Specification_ Rev1.3, page 10.
Change-Id: I0112a85f557826b629109e212dbbc752aeda305d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15202
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
| src/include/spd.h | diffblobblamehistory |