| commit | 43fd0402265c0c1381fc3fcf04610ed9f2781f2f | |
| author | Bernardo Perez Priego <bernardo.perez.priego@intel.com> | |
| Wed, 23 Jun 2021 00:59:38 +0000 (22 17:59 -0700) | ||
| committer | Werner Zeh <werner.zeh@siemens.com> | |
| Mon, 28 Jun 2021 04:26:53 +0000 (28 04:26 +0000) | ||
| tree | d56ea00ec8a9082c26a9f5d0e0dcac349811c7b7 | treesnapshot (tar.gz zip) |
| parent | fa6d31f9997278714d409512b0f77acbf55b32e2 | commitdiff |
mb/intel/adlrvp_m: Enable TCSS USB ports device path
This provide a more consistent mechanism to enable corresponding USB
TCSS port.
BUG=b:182960979
TEST=Boot device, Type C port should operate correctly.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: Iadc0df2e6e19a5afacbb7db1ae0bc7546dbcdc1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55772
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This provide a more consistent mechanism to enable corresponding USB
TCSS port.
BUG=b:182960979
TEST=Boot device, Type C port should operate correctly.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: Iadc0df2e6e19a5afacbb7db1ae0bc7546dbcdc1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55772
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| src/mainboard/intel/adlrvp/devicetree_m.cb | diffblobblamehistory |