| commit | 43d2527203121be776d3e532c09ca46c2a8afaf9 | |
| author | Michael Niewöhner <foss@mniewoehner.de> | |
| Tue, 17 Sep 2019 16:48:00 +0000 (17 18:48 +0200) | ||
| committer | Patrick Georgi <pgeorgi@google.com> | |
| Wed, 20 Nov 2019 13:35:29 +0000 (20 13:35 +0000) | ||
| tree | 36f892e7a7d25d04c08e4690b1018db085d88e9e | treesnapshot (tar.gz zip) |
| parent | 8370f6b79c06bcea1a04f53e9028d0aa447e3583 | commitdiff |
soc/intel/skylake: lockdown: lock global reset
There are four chipsets selecting PMC_GLOBAL_RESET_ENABLE_LOCK but only
one (apollolake) is actually calling the code. Add the missing call.
Also fix the register offset in a comment in reset code.
Tested successfully on X11SSM-F by reading ETR3.
Change-Id: If190c3c66889ede105d958b423b38ebdcb698332
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36573
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are four chipsets selecting PMC_GLOBAL_RESET_ENABLE_LOCK but only
one (apollolake) is actually calling the code. Add the missing call.
Also fix the register offset in a comment in reset code.
Tested successfully on X11SSM-F by reading ETR3.
Change-Id: If190c3c66889ede105d958b423b38ebdcb698332
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36573
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| src/soc/intel/skylake/lockdown.c | diffblobblamehistory | |
| src/soc/intel/skylake/reset.c | diffblobblamehistory |