| commit | 436eac827aea4839169f2421006df42b8c5c379f | |
| author | Mario Scheithauer <mario.scheithauer@siemens.com> | |
| Fri, 12 Nov 2021 10:28:15 +0000 (12 11:28 +0100) | ||
| committer | Felix Held <felix-coreboot@felixheld.de> | |
| Mon, 15 Nov 2021 11:19:50 +0000 (15 11:19 +0000) | ||
| tree | 285ac152c1dc60de53adce4d1a67e96d2d6fc20d | treesnapshot (tar.gz zip) |
| parent | ed784bc0a79ce1c296a2685f22cb269d510403dd | commitdiff |
mb/siemens/mc_ehl2: Adjust PCIe clock source settings in devicetree
With latest hardware revision all clock outputs will be used on this
mainboard. For this reason set all clock source mappings to
'PCIE_CLK_FREE' to have a free running clock.
Change-Id: Ic3f6fb4e24128742ed72dade7a4555c39fb722ae
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
With latest hardware revision all clock outputs will be used on this
mainboard. For this reason set all clock source mappings to
'PCIE_CLK_FREE' to have a free running clock.
Change-Id: Ic3f6fb4e24128742ed72dade7a4555c39fb722ae
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
| src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb | diffblobblamehistory |