| commit | 421ce56f833edcfe34788ff07ebf5e09d582ff9f | |
| author | Bernardo Perez Priego <bernardo.perez.priego@intel.com> | |
| Wed, 9 Jun 2021 16:40:31 +0000 (9 09:40 -0700) | ||
| committer | Patrick Georgi <pgeorgi@google.com> | |
| Fri, 2 Jul 2021 07:47:50 +0000 (2 07:47 +0000) | ||
| tree | ae19123e015c16ba27955289b0b22c7330079ee5 | treesnapshot (tar.gz zip) |
| parent | 2033afa68263834906e3eed8b3215dbd8b9bdb97 | commitdiff |
soc/intel/alderlake: Add USB TCSS enablement
In order to detect USB Type C device port as Super Speed, we need to set
corresponding bit in UPD UsbTcPortEn. This patch will use device path
to determine which port should be enabled.
BUG=b:184324979
Test=Boot board, USB Type C must be functional and operate at Super Speed.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I7da63f21d51889a888699540f780cb26b480c26d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
In order to detect USB Type C device port as Super Speed, we need to set
corresponding bit in UPD UsbTcPortEn. This patch will use device path
to determine which port should be enabled.
BUG=b:184324979
Test=Boot board, USB Type C must be functional and operate at Super Speed.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I7da63f21d51889a888699540f780cb26b480c26d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
| src/soc/intel/alderlake/fsp_params.c | diffblobblamehistory |