| commit | 41d107019b6bcbdad80a1d76abca7a181fd339d5 | |
| author | Angel Pons <th3fanbus@gmail.com> | |
| Wed, 8 Sep 2021 13:23:22 +0000 (8 15:23 +0200) | ||
| committer | Matt DeVillier <matt.devillier@gmail.com> | |
| Tue, 16 Apr 2024 01:46:42 +0000 (16 01:46 +0000) | ||
| tree | a61c836cb2f7f3eed815ae340de95ad5e92cbdc9 | treesnapshot (tar.gz zip) |
| parent | 6ef23316c235d14213d0bdc48c6853d3059a0b64 | commitdiff |
sb/intel/lynxpoint: Fix AER and L1 sub-state reporting
Program the AER capability header register in a single write because
it's write-once. In addition, only PCH-LP supports L1 sub-states, so
only report the L1 sub-state capability on PCH-LP. This follows what
Lynx Point PCH reference code version 1.9.1 does.
Change-Id: I08bd107eec7a3b2f1701c4657ae104e0818ae035
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57503
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Program the AER capability header register in a single write because
it's write-once. In addition, only PCH-LP supports L1 sub-states, so
only report the L1 sub-state capability on PCH-LP. This follows what
Lynx Point PCH reference code version 1.9.1 does.
Change-Id: I08bd107eec7a3b2f1701c4657ae104e0818ae035
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57503
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| src/southbridge/intel/lynxpoint/pcie.c | diffblobblamehistory |