| commit | 40b41826e125fd726cec1369676d53704add3a0b | |
| author | Nick Vaccaro <nvaccaro@google.com> | |
| Wed, 7 Nov 2018 21:19:36 +0000 (7 13:19 -0800) | ||
| committer | Patrick Georgi <pgeorgi@google.com> | |
| Fri, 16 Nov 2018 12:32:20 +0000 (16 12:32 +0000) | ||
| tree | 307d9c472f5daa2972d7026e248d51ae0535f922 | treesnapshot (tar.gz zip) |
| parent | a5f5790c937915577f02555fe1aa1dc4cc206d2d | commitdiff |
mb/google/poppy/variant/atlas: config GPP_F10 to use PLTRST
GPIO's that use GPI_APIC setting with DEEP causes an IRQ storm after
S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic
reset over PLTRST to prevent IRQ storm after S3 resume and hence
configuring GPP_F10 (HP_IRQ_GPIO) to use PLTRST.
BUG=none
TEST=none
Change-Id: Idc6c42cb4dc6e8eb368d605c83f584f4c69077dc
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/29540
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPIO's that use GPI_APIC setting with DEEP causes an IRQ storm after
S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic
reset over PLTRST to prevent IRQ storm after S3 resume and hence
configuring GPP_F10 (HP_IRQ_GPIO) to use PLTRST.
BUG=none
TEST=none
Change-Id: Idc6c42cb4dc6e8eb368d605c83f584f4c69077dc
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/29540
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| src/mainboard/google/poppy/variants/atlas/gpio.c | diffblobblamehistory |