| commit | 3f689ca24ac93d28c5f564209edab7087b14744a | |
| author | Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> | |
| Mon, 21 Jan 2019 09:53:55 +0000 (21 15:23 +0530) | ||
| committer | Duncan Laurie <dlaurie@chromium.org> | |
| Wed, 23 Jan 2019 17:28:38 +0000 (23 17:28 +0000) | ||
| tree | d42eeaa4928401d34a02e6dd4c12285529611b2c | treesnapshot (tar.gz zip) |
| parent | 8adbec26be1f0ad8f8f06af59754dcedd126eecb | commitdiff |
mb/google/sarien: Replace B0D4 with TCPU
Replace B0D4 with TCPU for DPTF thermal sensor. This helps to
maintain consistency between coreboot and UEFI BIOS.
Change-Id: I024068c19160e1c08badef3d304ada14455c045f
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31028
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace B0D4 with TCPU for DPTF thermal sensor. This helps to
maintain consistency between coreboot and UEFI BIOS.
Change-Id: I024068c19160e1c08badef3d304ada14455c045f
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31028
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl | diffblobblamehistory | |
| src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl | diffblobblamehistory |