| commit | 3e666898cd99f4e15a39e360bb594d499e738b2d | |
| author | Ronak Kanabar <ronak.kanabar@intel.com> | |
| Mon, 23 Mar 2020 11:47:47 +0000 (23 17:17 +0530) | ||
| committer | Furquan Shaikh <furquan@google.com> | |
| Tue, 31 Mar 2020 18:07:40 +0000 (31 18:07 +0000) | ||
| tree | 3d30525f11bae4ad400b565e184451c0cc31b420 | treesnapshot (tar.gz zip) |
| parent | 45808399fc04e7c623af6ee1e7c7686fab09e790 | commitdiff |
vendorcode/intel/fsp: Update FSP header for Tiger Lake
Update FSPM header to include DisableDimmCh Upds for Tiger Lake
platform version 2457.
BUG=b:152000235
BRANCH=none
TEST="Build and Boot on Ripto/Volteer"
Change-Id: Ic743cb2134e6273a63c1212506c81ccbbdec442a
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Update FSPM header to include DisableDimmCh Upds for Tiger Lake
platform version 2457.
BUG=b:152000235
BRANCH=none
TEST="Build and Boot on Ripto/Volteer"
Change-Id: Ic743cb2134e6273a63c1212506c81ccbbdec442a
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
| src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h | diffblobblamehistory |