| commit | 39736253d573ce6b5afc7299013f303ae9537b81 | |
| author | Bora Guvendik <bora.guvendik@intel.com> | |
| Mon, 3 May 2021 21:06:16 +0000 (3 14:06 -0700) | ||
| committer | Patrick Georgi <pgeorgi@google.com> | |
| Wed, 12 May 2021 08:01:19 +0000 (12 08:01 +0000) | ||
| tree | 3673acff77489aca265de31a10cf781681a3eab8 | treesnapshot (tar.gz zip) |
| parent | 918e5352b747fe08158f0bc06975342024e385f0 | commitdiff |
mb/intel/adlrvp_m: Program CPU PCIE RP GPIOs in early GPIO
We need to configure CPU PCIE root port related gpios in early
boot block stage for CPU root ports to work due to the dependency on
FSP-M PCIe configuration. Since we're removing this programming from
FSP, coreboot needs to take care of programming this GPIOs. Also we
need to enable virtual wire messaging for native gpios for CPU PCIE
root ports.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I27c898943471d834bd82e3c7e8b36cceb12de099
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52865
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We need to configure CPU PCIE root port related gpios in early
boot block stage for CPU root ports to work due to the dependency on
FSP-M PCIe configuration. Since we're removing this programming from
FSP, coreboot needs to take care of programming this GPIOs. Also we
need to enable virtual wire messaging for native gpios for CPU PCIE
root ports.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I27c898943471d834bd82e3c7e8b36cceb12de099
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52865
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| src/mainboard/intel/adlrvp/early_gpio_m.c | diffblobblamehistory |