| commit | 344f68be108fca3b9fe8e4280ce8015f1dd8c8e1 | |
| author | Tan, Lean Sheng <lean.sheng.tan@intel.com> | |
| Fri, 27 Nov 2020 13:33:08 +0000 (27 05:33 -0800) | ||
| committer | Werner Zeh <werner.zeh@siemens.com> | |
| Thu, 10 Dec 2020 10:49:15 +0000 (10 10:49 +0000) | ||
| tree | 79cc2534dcd092eec085a93e91f9fd51f594d3df | treesnapshot (tar.gz zip) |
| parent | ed42c7ef515edb1a017b837f8e6d26b801e8d2df | commitdiff |
mb/intel/ehlcrb: Add EHL CRB memory initialization support
Update memory parameters based on memory type supported by
Elkhart Lake CRB:
1. Update spd data for EHL LPDDR4X memory
- DQ byte map
- DQS CPU-DRAM map
- Rcomp resistor
- Rcomp target
2. Add configurations for vref_ca & interleaved memory
3. Add EHL CRB on board LPDDR4X SPD data bin file
4. Update mainboard related FSPM UPDs as part of memory
initialization
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: Ifd85caa9ac1c9baf443734eb17ad5683ee92ca3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Update memory parameters based on memory type supported by
Elkhart Lake CRB:
1. Update spd data for EHL LPDDR4X memory
- DQ byte map
- DQS CPU-DRAM map
- Rcomp resistor
- Rcomp target
2. Add configurations for vref_ca & interleaved memory
3. Add EHL CRB on board LPDDR4X SPD data bin file
4. Update mainboard related FSPM UPDs as part of memory
initialization
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: Ifd85caa9ac1c9baf443734eb17ad5683ee92ca3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>