| commit | 3398f3152cf005d1e8219feacac1e1ec4fe50095 | |
| author | CK Hu <ck.hu@mediatek.com> | |
| Tue, 16 Jun 2020 03:54:38 +0000 (16 11:54 +0800) | ||
| committer | Hung-Te Lin <hungte@chromium.org> | |
| Fri, 23 Oct 2020 03:58:45 +0000 (23 03:58 +0000) | ||
| tree | a48952d88a85c011e4f401d4fd821c2e6d268a9e | treesnapshot (tar.gz zip) |
| parent | 9190345bf071261a0764c9cfbe1472f974e2bd19 | commitdiff |
soc/mediatek/mt8192: Turn off L2C SRAM and reconfigure as L2 cache
Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready.
After DRAM is ready, we should invoke disable_l2c_sram to reconfigure
the L2C SRAM as L2 cache.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: Icaf80bd9da3e082405ba66ef05dd5ea9185784a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46387
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready.
After DRAM is ready, we should invoke disable_l2c_sram to reconfigure
the L2C SRAM as L2 cache.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: Icaf80bd9da3e082405ba66ef05dd5ea9185784a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46387
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| src/soc/mediatek/mt8192/Makefile.inc | diffblobblamehistory | |
| src/soc/mediatek/mt8192/mmu_operations.c | [new file with mode: 0644] | blob |
| src/soc/mediatek/mt8192/soc.c | diffblobblamehistory |