| commit | 302dddf0f48acce1c00ae04606b0bf56c7da3f9d | |
| author | Hung-Te Lin <hungte@chromium.org> | |
| Wed, 7 Aug 2019 22:28:43 +0000 (8 06:28 +0800) | ||
| committer | Julius Werner <jwerner@chromium.org> | |
| Tue, 13 Aug 2019 02:37:18 +0000 (13 02:37 +0000) | ||
| tree | fb96c4bdf5e7ef7724763a49af01d1513d07e95a | treesnapshot (tar.gz zip) |
| parent | 61e346624a2c8b7e3de5313f2f4bfa2d4359e660 | commitdiff |
soc/mediatek: dsi: Refactor MIPI TX configuration
The only platform-specific difference in mtk_dsi_phy_clk_setting is how
to configure MIPI TX because those registers (and logic) are quite
different across different SOCs.
The calculation of data rate is actually the same so we should isolate
it and move to common, and rename mtk_dsi_phy_clk_setting to a better
name as mtk_dsi_configure_mipi_tx.
BUG=b:80501386,b:117254947
TEST=make -j # board = oak and boots
Change-Id: I894dc2c4c053267debf5a58313b2bb489bcf5f3a
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The only platform-specific difference in mtk_dsi_phy_clk_setting is how
to configure MIPI TX because those registers (and logic) are quite
different across different SOCs.
The calculation of data rate is actually the same so we should isolate
it and move to common, and rename mtk_dsi_phy_clk_setting to a better
name as mtk_dsi_configure_mipi_tx.
BUG=b:80501386,b:117254947
TEST=make -j # board = oak and boots
Change-Id: I894dc2c4c053267debf5a58313b2bb489bcf5f3a
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>