| commit | 2ef3b2df1f562610219444d913224d0600c097a1 | |
| author | Furquan Shaikh <furquan@google.com> | |
| Mon, 22 Jun 2020 05:27:19 +0000 (21 22:27 -0700) | ||
| committer | Furquan Shaikh <furquan@google.com> | |
| Thu, 25 Jun 2020 08:10:04 +0000 (25 08:10 +0000) | ||
| tree | 3ede558a643317670cc346a8e7859137d47fdec8 | treesnapshot (tar.gz zip) |
| parent | 8302585c152926c086107cdf11f48040d0d873d5 | commitdiff |
mb/google/zork: Move PCIE_RST0_L configuration to early GPIO table
This change moves the configuration of PCIE_RST0_L as native
function to happen in early GPIO table. This ensures that the PERST#
signal is deasserted as soon as possible when the system comes out
of sleep state in case the sleep path asserted/deasserted the PERST#
as GPIO out.
A big difference in functionality with this change is that PCIE_RST0_L
signal is now configured as part of RO, which should be fine since
all PCIe devices have a second AUX_RESET_L signal or use PCIE_RST1_L
to control the actual reset to the device.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I21a9c25b5a8a6d502cdb79cbe0dbad6ef98d6d63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42739
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change moves the configuration of PCIE_RST0_L as native
function to happen in early GPIO table. This ensures that the PERST#
signal is deasserted as soon as possible when the system comes out
of sleep state in case the sleep path asserted/deasserted the PERST#
as GPIO out.
A big difference in functionality with this change is that PCIE_RST0_L
signal is now configured as part of RO, which should be fine since
all PCIe devices have a second AUX_RESET_L signal or use PCIE_RST1_L
to control the actual reset to the device.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I21a9c25b5a8a6d502cdb79cbe0dbad6ef98d6d63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42739
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>