| commit | 2e073fc43934d376dcebe7c7a7e64d45384f21b1 | |
| author | Duncan Laurie <dlaurie@chromium.org> | |
| Mon, 17 Nov 2014 21:05:50 +0000 (17 13:05 -0800) | ||
| committer | Patrick Georgi <pgeorgi@google.com> | |
| Sat, 4 Apr 2015 10:40:24 +0000 (4 12:40 +0200) | ||
| tree | e815e7556c93cdd8e7d034028fdad86142973063 | treesnapshot (tar.gz zip) |
| parent | c1b52757d98ea60fbdd67ea99a8e9a26584b4970 | commitdiff |
broadwell: Add USB3 PHY tuning fields to PEI DATA
These are board specific adjustments that can be made for each
USB3 port.
BUG=chrome-os-partner:28234
BRANCH=samus,auron
TEST=build and boot on samus
Change-Id: Iaa3ce09419dfd64e3e8187f6dc073a8c68565337
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 21000496bb4560c9d1452a128335bbf24ca1b0aa
Original-Change-Id: Iab92ff7b0218d4abd9eba8a94d34ddd9a30ddb87
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/230231
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9275
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
These are board specific adjustments that can be made for each
USB3 port.
BUG=chrome-os-partner:28234
BRANCH=samus,auron
TEST=build and boot on samus
Change-Id: Iaa3ce09419dfd64e3e8187f6dc073a8c68565337
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 21000496bb4560c9d1452a128335bbf24ca1b0aa
Original-Change-Id: Iab92ff7b0218d4abd9eba8a94d34ddd9a30ddb87
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/230231
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9275
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
| src/soc/intel/broadwell/broadwell/pei_data.h | diffblobblamehistory |