| commit | 2d69d75749b7c320fec9c50403add0cea3272687 | |
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | |
| Thu, 2 Nov 2017 22:55:44 +0000 (2 16:55 -0600) | ||
| committer | Aaron Durbin <adurbin@chromium.org> | |
| Wed, 8 Nov 2017 19:23:49 +0000 (8 19:23 +0000) | ||
| tree | f13fdc9a2c104a8511de736b554394efbab18eab | treesnapshot (tar.gz zip) |
| parent | b838256a51b3d58f297165b5d238ea35aba3bce7 | commitdiff |
amd/stoneyridge: Add northbridge register macros
Add helpers for determining the D18F1 offset for MMIO base and limit,
and I/O base/limit registers.
Change-Id: I3f61bff00b8f3ada3e1bbfb163e1f223708bd47d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add helpers for determining the D18F1 offset for MMIO base and limit,
and I/O base/limit registers.
Change-Id: I3f61bff00b8f3ada3e1bbfb163e1f223708bd47d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| src/soc/amd/stoneyridge/include/soc/northbridge.h | diffblobblamehistory |