mb/google/volteer/var/volteer: Use auto-generated Makefile.inc using gen_part_id.go

mb/google/volteer/var/volteer: Use auto-generated Makefile.inc using gen_part_id.go

This change adds mem_list_variant.txt that contains the list of
memory parts used by volteer and Makefile.inc generated by
gen_part_id.go using mem_list_variant.txt.

In the final change of the series, all volteer variants will be
switched from using the current SPDs to new auto-generated SPDs.

Differences in auto-generated SPD from current SPD are as follows:

Part: K4U6E3S4AA-MGCL
Byte#    Current     New         Explanation
6        0x95        0x94        Signal loading is not used by
                                 MRC. Set bits 1:0 to 00.
16       0x48        0x00        Signal loading is not used by
                                 MRC. Set to 0x00.
19       0x0F        0xFF        As per JEDEC spec, tckMax should be
                                 100ns. So, value should be 0xff as
                                 per datasheet.
21,22    0x55,0x00   0x54,0x05   As per datasheet, part supports CAS
                                 latencies 20,24,28,32,36. So value
                                 should be 0x54, 0x05.
24       0x8C        0x87        taa is .468ns * CAS-36 which results
                                 in byte 24 being 0x87 as per datasheet.
123      0x00        0xE5        Fine offset for taa. Expected value
                                 is 0xE5 as per datasheet.
124      0x7F        0x00        Fine offset for tckMax. Expected
                                 value is 0x00 as per datasheet.
125      0xE1        0xE0        Fine offset for tckMin. As per
                                 datasheet tckMin is 0.468ns. So, this
                                 comes out to be 0xE0.

Part: K4UBE3D4AA-MGCL
Byte#    Current     New         Explanation
6        0xB5        0xB4        Signal loading is not used by
                                 MRC. Set bits 1:0 to 00.
16       0x48        0x00        Signal loading is not used by
                                 MRC. Set to 0x00.
19       0x0F        0xFF        As per JEDEC spec, tckMax should be
                                 100ns. So, value should be 0xff as
                                 per datasheet.
123      0x00        0xE5        Fine offset for taa. Expected value
                                 is 0xE5 as per datasheet.

Part: H9HCNNNBKMMLXR-NEE
Byte#    Current     New         Explanation
6        0x95        0x94        Signal loading is not used by
                                 MRC. Set bits 1:0 to 00.
16       0x48        0x00        Signal loading is not used by
                                 MRC. Set to 0x00.
19       0x0F        0xFF        As per JEDEC spec, tckMax should be
                                 100ns. So, value should be 0xff as
                                 per datasheet.
21,22    0x55,0x00   0x54,0x05   As per datasheet, part supports CAS
                                 latencies 20,24,28,32,36. So value
                                 should be 0x54, 0x05.
24       0x8C        0x87        taa is .468ns * CAS-36 which results
                                 in byte 24 being 0x87 as per datasheet.
123      0x00        0xE5        Fine offset for taa. Expected value
                                 is 0xE5 as per datasheet.
124      0x7F        0x00        Fine offset for tckMax. Expected
                                 value is 0x00 as per datasheet.
125      0xE1        0xE0        Fine offset for tckMin. tckMin is
                                 calculated as (1/4267)*2 which comes
                                 out to be 0.46871. Some datasheets
                                 round this down to 0.468 and others
                                 round it up to 0.469. JEDEC spec uses
                                 0.468. As per that, this value comes
                                 out to be 0xE0.

Part: H9HCNNNFAMMLXR-NEE
Byte#    Current     New         Explanation
4        0x15        0x16        As per datasheet, density is 16Gb per
                                 logical channel. So value should be 0x16.
6        0xF9        0xB8        This device has 4 logical dies
                                 instead of 8. Also, signal loading is
                                 not used by MRC.
16       0x48        0x00        Signal loading is not used by
                                 MRC. Set to 0x00.
20,21,   0x92,0x55,  0x12,0x29,  As per datasheet, part supports CAS
22       0x00        0x15        latencies 6,10,16,22,26,32,36,40. So value
                                 should be 0x12,0x29,0x15.
24       0x8C        0x96        taa is .468ns * CAS-40 which results
                                 in byte 24 being 0x96 as per datasheet.
29,30    0xE0,0x0B   0xC0,0x08   As per datasheet, this corresponds to
                                 280ns in MTB units which is 0x08C0.
31,32    0xF0,0x05   0x60,0x04   As per datasheet, this corresponds to
                                 140ns in MTB units which is 0x04C0.
123      0x00        0xE2        Fine offset for taa. Expected value
                                 is 0xE2 as per datasheet.
124      0x7F        0x00        Fine offset for tckMax. Expected
                                 value is 0x00 as per datasheet.
125      0xE1        0xE0        Fine offset for tckMin. tckMin is
                                 calculated as (1/4267)*2 which comes
                                 out to be 0.46871. Some datasheets
                                 round this down to 0.468 and others
                                 round it up to 0.469. JEDEC spec uses
                                 0.468. As per that, this value comes
                                 out to be 0xE0.

Part: MT53E1G32D2NP-046 WT:A
Byte#    Current     New         Explanation
4        0x15        0x16        As per datasheet, density is 16Gb per
                                 logical channel. So value should be 0x16.
5        0x21        0x29        As per datasheet, this part has 17row
                                 address bits and 10column address
                                 bits. This results in 0x29.
6        0xB5        0x94        This device has 2 logical dies. Also,
                                 MRC does not use signal loading.
16       0x48        0x00        Signal loading is not used by
                                 MRC. Set to 0x00.
12       0x0A        0x02        As per datasheet, this is 1rank and
                                 16-bit wide channel. So, value should
                                 be 0x02.
21,22    0x55,0x00   0x54,0x05   As per datasheet, part supports CAS
                                 latencies 20,24,28,32,36. So value
                                 should be 0x54, 0x05.
24       0x8C        0x87        taa is .468ns * CAS-36 which results
                                 in byte 24 being 0x87 as per datasheet.
29,30    0xC0,0x08   0xE0,0x0B   As per datasheet, this corresponds to
                                 380ns in MTB units which is 0x0BE0.
31,32    0x60,0x04   0xF0,0x05   As per datasheet, this corresponds to
                                 190ns in MTB units which is 0x05F0.
123      0x00        0xE5        Fine offset for taa. Expected value
                                 is 0xE5 as per datasheet.
124      0x7F        0x00        Fine offset for tckMax. Expected
                                 value is 0x00 as per datasheet.
125      0xE1        0xE0        Fine offset for tckMin. As per
                                 datasheet tckMin is 0.468ns. So, this
                                 comes out to be 0xE0.
BUG=b:147321551,b:155423877

Change-Id: I3998b2cd91020130bacf371fce9b0d307304acbe
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>