| commit | 282e75b118425e932ada6c36855bbe7fd66e4747 | |
| author | John Zhao <john.zhao@intel.com> | |
| Wed, 31 Mar 2021 00:17:26 +0000 (30 17:17 -0700) | ||
| committer | Patrick Georgi <pgeorgi@google.com> | |
| Tue, 6 Apr 2021 07:04:26 +0000 (6 07:04 +0000) | ||
| tree | fb344f974d8d8cd6639e5457083dff3c7ddd91f4 | treesnapshot (tar.gz zip) |
| parent | 9922304b35e6b43b673cbb46e32f9fbe9bc47562 | commitdiff |
soc/intel/alderlake: Update variable SD3C to only track enabled devices
Each TCSS DMA is grouped together with two PCIe RPs in terms of PM flow.
This change ensures that SD3C is updated for the TCSS DMA devices
corresponding to the TBT RP ports. If TBT port is 0 or 1, SD3C for DMA0
is updated, else for DMA1.
BUG=None
TEST=Built Alderlake image successfully.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ia3462dfbb287a374960a57bb4c3541db2a435611
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51965
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Each TCSS DMA is grouped together with two PCIe RPs in terms of PM flow.
This change ensures that SD3C is updated for the TCSS DMA devices
corresponding to the TBT RP ports. If TBT port is 0 or 1, SD3C for DMA0
is updated, else for DMA1.
BUG=None
TEST=Built Alderlake image successfully.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ia3462dfbb287a374960a57bb4c3541db2a435611
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51965
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| src/soc/intel/alderlake/acpi/tcss_pcierp.asl | diffblobblamehistory |