| commit | 27fdfc60bc3b5ab1c2e59599d54093bbb25d37a7 | |
| author | Michał Żygowski <michal.zygowski@3mdeb.com> | |
| Thu, 7 Apr 2022 13:03:09 +0000 (7 15:03 +0200) | ||
| committer | Felix Held <felix-coreboot@felixheld.de> | |
| Tue, 3 May 2022 19:36:42 +0000 (3 19:36 +0000) | ||
| tree | fc398b74615479f0f6a7b8fae1b10bea226d906b | treesnapshot (tar.gz zip) |
| parent | 86221c63aefeec10571a4698e74737af80c0539f | commitdiff |
soc/intel/alderlake: Update maximum PCIe and TBT ports and clocks
ADL-S CPU has maximum 3 PCIe interfaces when the x16 link is bifurcated
into two x8 links. ADL-S PCH has up to 28 PCIe Root Ports, 18 CLKOUT and
CLKREQ signals. ADL-S CPUs do not have Thunderbolt.
Based on the Intel DOC #619501 and #619362.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I408c815d5a43c081beb3f84d795c2b863ce33eb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
ADL-S CPU has maximum 3 PCIe interfaces when the x16 link is bifurcated
into two x8 links. ADL-S PCH has up to 28 PCIe Root Ports, 18 CLKOUT and
CLKREQ signals. ADL-S CPUs do not have Thunderbolt.
Based on the Intel DOC #619501 and #619362.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I408c815d5a43c081beb3f84d795c2b863ce33eb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
| src/soc/intel/alderlake/Kconfig | diffblobblamehistory |