| commit | 23e8b5b4949063319c339120f13e392a90493b58 | |
| author | John Zhao <john.zhao@intel.com> | |
| Thu, 28 May 2020 06:11:19 +0000 (27 23:11 -0700) | ||
| committer | Furquan Shaikh <furquan@google.com> | |
| Sat, 30 May 2020 00:42:15 +0000 (30 00:42 +0000) | ||
| tree | 89a760ede3520fb5ece385e3797784d5cd7b27ae | treesnapshot (tar.gz zip) |
| parent | 74b1919f1779a3a3b1a0320482784bb31234b175 | commitdiff |
soc/intel/tigerlake: Configure TcssDma0En and TcssDma1En
Determine the TcssDma0 and TcssDma1 enabling based on TBT DMA
controllers setting.
BUG=:b:146624360
TEST=Booted on Volteer and verified TcssDma0 and TcssDma1 enabling.
lspci shows TcssDma0(0d.2) and TcssDma1(0d.3).
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I61ac4131481374e9a2a34d1a30f822046c3897fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41812
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Determine the TcssDma0 and TcssDma1 enabling based on TBT DMA
controllers setting.
BUG=:b:146624360
TEST=Booted on Volteer and verified TcssDma0 and TcssDma1 enabling.
lspci shows TcssDma0(0d.2) and TcssDma1(0d.3).
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I61ac4131481374e9a2a34d1a30f822046c3897fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41812
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| src/soc/intel/tigerlake/chip.h | diffblobblamehistory | |
| src/soc/intel/tigerlake/romstage/fsp_params.c | diffblobblamehistory |