| commit | 2326a284ac6a6646a918331425952ece2da723c1 | |
| author | Philipp Hug <philipp@hug.cx> | |
| Sat, 7 Jul 2018 13:54:37 +0000 (7 15:54 +0200) | ||
| committer | Ronald G. Minnich <rminnich@gmail.com> | |
| Fri, 14 Sep 2018 14:33:09 +0000 (14 14:33 +0000) | ||
| tree | d83f6fc80597a33132895edd356171547c753343 | treesnapshot (tar.gz zip) |
| parent | 2912e8e5dc66708703db79df87e3215408a653ae | commitdiff |
riscv: add trampoline in MBR block to support boot mode 1
Add "j pc + 0x0800" at the beginning of the MBR to jump to bootblock.
Tested on hardware:
boot mode 15: works as before
boot mode 1: jump to bootblock works, but bootblock needs to be modified to
move the stack to L2LIM. This will be in a separate commit.
Further changes are needed in the bootblock
Change-Id: I16e762d9f027346b124412f1f7ee6ff37f431d86
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/27397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Add "j pc + 0x0800" at the beginning of the MBR to jump to bootblock.
Tested on hardware:
boot mode 15: works as before
boot mode 1: jump to bootblock works, but bootblock needs to be modified to
move the stack to L2LIM. This will be in a separate commit.
Further changes are needed in the bootblock
Change-Id: I16e762d9f027346b124412f1f7ee6ff37f431d86
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/27397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
| Documentation/mainboard/sifive/hifive-unleashed.md | diffblobblamehistory | |
| util/riscv/sifive-gpt.py | diffblobblamehistory |