| commit | 21573e9f4e6c5ec1c5ab7da265f42642f832394b | |
| author | Lijian Zhao <lijian.zhao@intel.com> | |
| Thu, 9 Nov 2017 03:21:32 +0000 (8 19:21 -0800) | ||
| committer | Aaron Durbin <adurbin@chromium.org> | |
| Mon, 20 Nov 2017 17:13:57 +0000 (20 17:13 +0000) | ||
| tree | d0d7b3d22cd2d551af87703ec0cd9f3373132e97 | treesnapshot (tar.gz zip) |
| parent | afd03d8a28df60a058e73e4f1f4e0e89f8373bd1 | commitdiff |
soc/intel/cannonlake: Add ACPI workaround for EMMC
Two W/A had been added here for EMMC to make it working properly.
1. Enable power gating after D3 entry, disable power gating before D0
entry.
2. Add 50 ms delay to ensure Rcomp calibration done before EMMC out of
D3.
BUG=b:69323943
TEST=Run multiple ACPI S3 cycles on cannonlake u LPDDR4 platform.
Change-Id: Ic6e98264521fb02b911a8c157a7982afa35fe20c
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Two W/A had been added here for EMMC to make it working properly.
1. Enable power gating after D3 entry, disable power gating before D0
entry.
2. Add 50 ms delay to ensure Rcomp calibration done before EMMC out of
D3.
BUG=b:69323943
TEST=Run multiple ACPI S3 cycles on cannonlake u LPDDR4 platform.
Change-Id: Ic6e98264521fb02b911a8c157a7982afa35fe20c
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| src/soc/intel/cannonlake/acpi/scs.asl | diffblobblamehistory |