| commit | 1c6ea92e6fcee21aa01a20500594a09ab14caa74 | |
| author | Michael Niewöhner <foss@mniewoehner.de> | |
| Sat, 2 Nov 2019 11:20:53 +0000 (2 12:20 +0100) | ||
| committer | Patrick Georgi <pgeorgi@google.com> | |
| Wed, 20 Nov 2019 13:35:08 +0000 (20 13:35 +0000) | ||
| tree | b03c96ef794a6f2ba7383d4261e2826b9d8a350d | treesnapshot (tar.gz zip) |
| parent | 35e76dde7708d0646c56eaf3b5c063b27d2add62 | commitdiff |
soc/intel/common: pmclib: make use of the new ETR address API
Make use of the new ETR address API in the ETR3 register related
functions.
Further, disabling and locking of global reset is now done at once to
save one read-modify-write cycle, thus the function was renamed
accordingly and the now redundant disabling in soc/apl got removed.
Change-Id: I49f59efb4a7c7d3d629ac54a7922bbcc8a87714d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Make use of the new ETR address API in the ETR3 register related
functions.
Further, disabling and locking of global reset is now done at once to
save one read-modify-write cycle, thus the function was renamed
accordingly and the now redundant disabling in soc/apl got removed.
Change-Id: I49f59efb4a7c7d3d629ac54a7922bbcc8a87714d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| src/soc/intel/apollolake/chip.c | diffblobblamehistory | |
| src/soc/intel/common/block/include/intelblocks/pmclib.h | diffblobblamehistory | |
| src/soc/intel/common/block/pmc/pmclib.c | diffblobblamehistory |