| commit | 19e7273ec2dc243b4089b9aeeaf7929ff5a20a34 | |
| author | Arthur Heymans <arthur@aheymans.xyz> | |
| Fri, 11 Jan 2019 22:56:51 +0000 (11 23:56 +0100) | ||
| committer | Arthur Heymans <arthur@aheymans.xyz> | |
| Tue, 15 Jan 2019 11:38:01 +0000 (15 11:38 +0000) | ||
| tree | 98894887d49e25e325f9d87eb9677e932d112400 | treesnapshot (tar.gz zip) |
| parent | 0feaa85233c099b06f84d5a0e1d82575efdba56b | commitdiff |
cpu/intel/socket_FCBGA559: Use the non-evict cache as ram setup
Pineview CPUs support a non-eviction mode that ought to be used
during cache as ram setup.
This assumes that all atoms that need to set a special register to
enable L2 cache are socketed and hence uses a static Kconfig option
to set that MSR on affected CPUs.
Tested on Foxconn D41S, still boots.
Change-Id: Iec943f5710314fb7a644d89dbd6d8c425f4ed735
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30863
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Pineview CPUs support a non-eviction mode that ought to be used
during cache as ram setup.
This assumes that all atoms that need to set a special register to
enable L2 cache are socketed and hence uses a static Kconfig option
to set that MSR on affected CPUs.
Tested on Foxconn D41S, still boots.
Change-Id: Iec943f5710314fb7a644d89dbd6d8c425f4ed735
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30863
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>