| commit | 18571389d5f6a3882ad0512ead712233a3a117a6 | |
| author | Angel Pons <th3fanbus@gmail.com> | |
| Sun, 28 Mar 2021 11:49:39 +0000 (28 13:49 +0200) | ||
| committer | Angel Pons <th3fanbus@gmail.com> | |
| Mon, 5 Apr 2021 13:01:37 +0000 (5 13:01 +0000) | ||
| tree | 6257f551a08027e5430ae0dddde8017cc87730ec | treesnapshot (tar.gz zip) |
| parent | afb3d7e7ecccdc1fbde66fe08252bd97de4df35d | commitdiff |
device/dram/ddr3: Rename DDR3 SPD memory types
To avoid name clashes with definitions for other DRAM generations,
rename the enum type and values to contain `ddr3` or `DDR3`.
Change-Id: If3710149ba94b94ed14f03e32f5e1533b4bc25c8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51896
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To avoid name clashes with definitions for other DRAM generations,
rename the enum type and values to contain `ddr3` or `DDR3`.
Change-Id: If3710149ba94b94ed14f03e32f5e1533b4bc25c8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51896
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| src/device/dram/ddr3.c | diffblobblamehistory | |
| src/include/device/dram/ddr3.h | diffblobblamehistory | |
| src/soc/intel/common/smbios.c | diffblobblamehistory |