| commit | 1848ba3b54dec516471a4a9fce4410ad62918b13 | |
| author | Arthur Heymans <arthur@aheymans.xyz> | |
| Tue, 11 Apr 2017 15:09:31 +0000 (11 17:09 +0200) | ||
| committer | Patrick Georgi <pgeorgi@google.com> | |
| Mon, 14 May 2018 07:40:26 +0000 (14 07:40 +0000) | ||
| tree | 42aa88e95ba2749876d3a0d1e25d56000af6586b | treesnapshot (tar.gz zip) |
| parent | 701da39fb7ab9c32e3885c5428b1ee28c6ca5e04 | commitdiff |
nb/x4x/raminit: Decode ddr3 dimms
Since this memory controller supports both DDR2 and DDR3 allow it to
decode both while making the dram type mutually exclusive.
Change-Id: I8dba19ca1e6e6b0a03b56c8de9633f9c1a2eb7d7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Since this memory controller supports both DDR2 and DDR3 allow it to
decode both while making the dram type mutually exclusive.
Change-Id: I8dba19ca1e6e6b0a03b56c8de9633f9c1a2eb7d7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
| src/northbridge/intel/x4x/raminit.c | diffblobblamehistory | |
| src/northbridge/intel/x4x/x4x.h | diffblobblamehistory |