| commit | 137f86149e37ff18b1837860aef1971eec06f0a1 | |
| author | Martin Roth <martin@coreboot.org> | |
| Wed, 24 Jun 2020 04:15:33 +0000 (23 22:15 -0600) | ||
| committer | Martin Roth <martinroth@google.com> | |
| Wed, 8 Jul 2020 20:42:07 +0000 (8 20:42 +0000) | ||
| tree | afaa581a0b047490807254be4bbee237aa6825f0 | treesnapshot (tar.gz zip) |
| parent | d09b9747e77e6309fbd53bd9b7260fce0e77867c | commitdiff |
soc/amd/common: Don't init SMIs or SCIs in psp_verstage
We can't set the SMI or SCI flags in psp verstage, so skip them.
TEST=Build
BUG=b:154142138
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I40eb464cde6b233607de1e177702c643ea2b4bb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42765
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We can't set the SMI or SCI flags in psp verstage, so skip them.
TEST=Build
BUG=b:154142138
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I40eb464cde6b233607de1e177702c643ea2b4bb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42765
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| src/soc/amd/common/block/gpio_banks/gpio.c | diffblobblamehistory |