| commit | 0da186c3ffb1d9aa7433a5d0d5263aba7a25ad60 | |
| author | Rizwan Qureshi <rizwan.qureshi@intel.com> | |
| Thu, 23 Feb 2017 09:13:39 +0000 (23 14:43 +0530) | ||
| committer | Furquan Shaikh <furquan@google.com> | |
| Sat, 4 Mar 2017 16:35:13 +0000 (4 17:35 +0100) | ||
| tree | bc766e52206f4cf2f3feeda7f06b45a8a45b7dc4 | treesnapshot (tar.gz zip) |
| parent | d55ea7b69e2aaa77ff15da0e26a4dbdcce8ac81d | commitdiff |
soc/intel/skylake: indicate voltage margining enabled/disabled
Support for voltage margining is dependent on the platform.
Enabling voltage margining puts additional constraints for
the SLP_S0# to be asserted and hence moving to S0ix state.
If the platform PMIC/VR supports PCH voltage reduction,
voltage marigining can be enabled.
Use the UPD provided by FSP to enable/disable voltage margining.
Change-Id: Iea214e9d7d6126e8367426485c6446ced63caa66
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/18469
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Support for voltage margining is dependent on the platform.
Enabling voltage margining puts additional constraints for
the SLP_S0# to be asserted and hence moving to S0ix state.
If the platform PMIC/VR supports PCH voltage reduction,
voltage marigining can be enabled.
Use the UPD provided by FSP to enable/disable voltage margining.
Change-Id: Iea214e9d7d6126e8367426485c6446ced63caa66
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/18469
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| src/soc/intel/skylake/chip.h | diffblobblamehistory | |
| src/soc/intel/skylake/chip_fsp20.c | diffblobblamehistory |