| commit | 0d5ac7440a1750169da3132d0e181a429d191002 | |
| author | nick_xr_chen <nick_xr_chen@wistron.corp-partner.google.com> | |
| Thu, 24 Sep 2020 13:42:42 +0000 (24 21:42 +0800) | ||
| committer | Patrick Georgi <pgeorgi@google.com> | |
| Mon, 28 Sep 2020 09:33:37 +0000 (28 09:33 +0000) | ||
| tree | e4c4615025be2bb43643a541eca775d8e0528853 | treesnapshot (tar.gz zip) |
| parent | 1f2c59b099fb5dd3dabcb835816171101ab2494b | commitdiff |
mb/google/volteer/variants/eldrid: Configure GPP_S4 and GPP_S5
GPP_S4 and GPP_S5 use as DMIC pins that need to be defined as NF2
BUG=b:168564129
Signed-off-by: nick_xr_chen <nick_xr_chen@wistron.corp-partner.google.com>
Change-Id: Ia1fca960ac85f253882f0aa68b370eed49ac67b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
GPP_S4 and GPP_S5 use as DMIC pins that need to be defined as NF2
BUG=b:168564129
Signed-off-by: nick_xr_chen <nick_xr_chen@wistron.corp-partner.google.com>
Change-Id: Ia1fca960ac85f253882f0aa68b370eed49ac67b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
| src/mainboard/google/volteer/variants/eldrid/gpio.c | diffblobblamehistory |