| commit | 0d590b7d915f47c2102b2515aca8b608205c4258 | |
| author | Cliff Huang <cliff.huang@intel.corp-partner.google.com> | |
| Fri, 29 Apr 2022 01:20:27 +0000 (28 18:20 -0700) | ||
| committer | Felix Held <felix-coreboot@felixheld.de> | |
| Thu, 9 Jun 2022 13:40:08 +0000 (9 13:40 +0000) | ||
| tree | 90028ccf76aac457885332d1878c47c94ace4970 | treesnapshot (tar.gz zip) |
| parent | 61a442ec01b1a7d9a2d83604956f8355ea391b3e | commitdiff |
soc/intel/alderlake: add support for external source clock
Support up to 10 PCIe source clock out, including source clock out 7, 8, 9.
This allows boards to use source clock 7, 8, 9.
BUG=b:233252409
BRANCH=firmware-brya-14505.B
Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: I0296974fb8557de1edea7f9ca2d96db0afd8a743
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63943
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Support up to 10 PCIe source clock out, including source clock out 7, 8, 9.
This allows boards to use source clock 7, 8, 9.
BUG=b:233252409
BRANCH=firmware-brya-14505.B
Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: I0296974fb8557de1edea7f9ca2d96db0afd8a743
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63943
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
| src/soc/intel/alderlake/Kconfig | diffblobblamehistory |